128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
®
MT28F128J3, MT28F640J3,
MT28F320J3
Q-FLASH MEMORY
Features
Figure 1: 56-Pin TSOP Type I
Memory Organization
• x8/x16
• One hundred twenty-eight 128KB erase blocks
(128Mb)
• Sixty-four 128KB erase blocks (64Mb)
• Thirty-two 128KB erase blocks (32Mb)
VCC, VCCQ, and VPEN voltages:
• 2.7V to 3.6V VCC operation
• 2.7V to 3.6V application programming
Interface Asynchronous Page Mode Reads:
• 120ns/25ns read access time (128Mb)
• 115ns/25ns read access time (64Mb)
• 110ns/25ns read access time (32Mb)
Manufacturer’s Identification Code (ManID)
• Micron® (0x2Ch)
• Intel® (0x89h)
Industry-standard pinout
Inputs and outputs are fully TTL-compatible
Common Flash Interface (CFI) and
Scalable Command Set
Automatic write and erase algorithm
5.6µs-per-byte effective programming time using write
buffer
128-bit protection register
• 64-bit unique device identifier
• 64-bit user-programmable OTP cells
Enhanced data protection feature with VPEN = VSS
• Flexible sector locking
• Sector erase/program lockout during power
transition
Security block features
Contact factory for availability
100,000 ERASE cycles per block
Automatic suspend options:
• Block Erase Suspend-to-Read
• Block Erase Suspend-to-Program
• Program Suspend-to-Read
Figure 2: 64-Ball FBGA
Options
Mark
Timing
• 110ns (32Mb)
• 115ns (64Mb)
• 120ns (128Mb)
Operating Temperature Range
• Extended Temperature: -40°C to +85°C
Packages
• 56-pin (standard) TSOP Type I
• 56-pin (lead-free) TSOP Type I
• 64-ball (standard) FBGA (1.00mm pitch)
• 64-ball (lead-free) FBGA (1.00mm pitch)
Manufacturer’s Identification Code (ManID)
• Micron (0x2Ch)
• Intel (0x89h)
-11
-115
-12
ET
RG
RP
FS
BS
M
Part Number Example:
MT28F640J3RG-115ET
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
‡
1
©2000 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
56-Pin TSOP Type I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
64-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Device Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Memory Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Reset/Power-Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Read Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Read Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
READ ARRAY Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
READ QUERY MODE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Query Structure Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Primary Vendor-Specific Extended-Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
READ IDENTIFIER CODES Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
READ STATUS REGISTER Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
CLEAR STATUS REGISTER Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
BLOCK ERASE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
BLOCK ERASE SUSPEND Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
WRITE-to-BUFFER Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
BYTE/WORD PROGRAM Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
PROGRAM SUSPEND Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SET READ CONFIGURATION Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
READ Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
STS CONFIGURATION Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
SET BLOCK LOCK BITS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
CLEAR BLOCK LOCK BITS Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
PROTECTION REGISTER PROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Reading the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Programming the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Locking the Protection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Five-Line Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
STS and Block Erase, Program, and Lock Bit Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Reducing Overshoots and Undershoots When Using Buffers or Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Vcc, Vpen, and RP# Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Power-Up/Down Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Electrical Specificatons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
List of Figures
Figure 1:
Figure 2:
Figure 3:
Figure 4:
Figure 5:
Figure 6:
Figure 7:
Figure 8:
Figure 9:
Figure 10:
Figure 11:
Figure 12:
Figure 13:
Figure 14:
Figure 15:
Figure 16:
Figure 17:
Figure 18:
Figure 19:
Figure 20:
Figure 21:
Figure 22:
Figure 23:
56-Pin TSOP Type I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
64-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pin and Ball Assignment Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Device Identifier Code Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
WRITE-to-BUFFER Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
BYTE/WORD PROGRAM Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
PROGRAM SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
BLOCK ERASE Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
BLOCK ERASE SUSPEND/RESUME Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
SET BLOCK LOCK BITS Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
CLEAR BLOCK LOCK BITS Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
PROTECTION REGISTER PROGRAMMING Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Transient Input/Output Reference Waveform for VccQ = 2.7V – 3.6V . . . . . . . . . . . . . . . . . . . . . . . . . .44
Transient Equivalent Test Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Page Mode and Standard Word/Byte READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
WRITE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
RESET Operation4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
56-Pin TSOP Type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
64-Ball FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
List of Tables
Table 1:
Table 2:
Table 3:
Table 4:
Table 5:
Table 6:
Table 7:
Table 8:
Table 9:
Table 10:
Table 11:
Table 12:
Table 13:
Table 14:
Table 15:
Table 16:
Table 17:
Table 18:
Table 19:
Table 20:
Table 21:
Table 22:
Table 23:
Table 24:
Table 25:
Table 26:
Table 27:
Table 28:
Table 29:
Table 30:
Pin/Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Chip-Enable Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Micron Q-Flash Memory Command Set Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Summary of Query-Structure Output as a Function of Device and Mode . . . . . . . . . . . . . . . . . . . . . . .16
Example: Query Structure Output of x16- and x8-Capable Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Query Structure1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Block Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
CFI Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Device Geometry Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Device Geometry Definition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Primary Vendor-Specific Extended-Query . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Burst READ Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Identifier Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Status Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Extended Status Register Definitions (XSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
Configuration Coding Definitions1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Word-Wide Protection Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Byte-Wide Protection Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Temperature and Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Recommended DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Test Configuration Loading Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
AC Characteristics–Read-Only Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
AC Characteristics – WRITE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Block Erase, Program, and Lock Bit Configuration Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
RESET Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
09005aef80b5a323
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5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
General Description
Micron’s even-sectored Q-Flash devices offer individual block locking that can lock and unlock a block
using the sector lock bits command sequence.
Status (STS) is a logic signal output that gives an
additional indicator of the internal state machine
(ISM) activity by providing a hardware signal of both
status and status masking. This status indicator minimizes central processing unit (CPU) overhead and system power consumption. In the default mode, STS acts
as an RY/BY# pin. When LOW, STS indicates that the
ISM is performing a block erase, program, or lock bit
configuration. When HIGH, STS indicates that the ISM
is ready for a new command.
Three chip enable (CE) pins are used for enabling
and disabling the device by activating the device’s
control logic, input buffer, decoders, and sense amplifiers.
BYTE# enables the device to be used in x8 or x16
read/write mode; BYTE# = 0 selects an 8-bit mode,
with address A0 selecting between the LOW and HIGH
byte, while BYTE# = 1 selects a 16-bit mode. When
BYTE# = 1, A1 becomes the lowest-order address line
with A0 being a no connect.
RP# is used to reset the device. When the device is
disabled and RP# is at VCC, the standby mode is
enabled. A reset time (tRWH) is required after RP#
switches HIGH until outputs are valid. Likewise, the
device has a wake time (tRS) from RP# HIGH until
writes to the command user interface (CUI) are recognized. When RP# is at GND, it provides write protection, resets the ISM, and clears the status register.
Variants of the MT28F320J3 and MT28F640J3
support the new security block lock features for
additional code security. (Contact factory for
availability.)
The MT28F320J3 is manufactured using 0.18µm
process technology, the MT28F128J3 and the
MT28F640J3 are manufactured using 0.15µm process
technology.
The MT28F128J3 is a nonvolatile, electrically blockerasable (Flash), programmable memory containing
134,217,728 bits organized as 16,777,218 bytes (8 bits)
or 8,388,608 words (16 bits). This 128Mb device is
organized as one hundred twenty-eight 128KB erase
blocks.
The MT28F640J3 contains 67,108,864 bits organized
as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits).
This 64Mb device is organized as sixty-four 128KB
erase blocks.
Similarly, the MT28F320J3 contains 33,554,432 bits
organized as 4,194,304 bytes (8 bits) or 2,097,152 words
(16 bits). This 32Mb device is organized as thirty-two
128KB erase blocks.
These three devices feature in-system block locking.
They also have common Flash interface (CFI) that permits software algorithms to be used for entire families
of devices. The software is device-independent, JEDEC
ID-independent with forward and backward compatibility.
Additionally, the scalable command set (SCS)
allows a single, simple software driver in all host systems to work with all SCS-compliant Flash memory
devices. The SCS provides the fastest system/device
data transfer rates and minimizes the device and system-level implementation costs.
To optimize the processor-memory interface, the
device accommodates VPEN, which is switchable during block erase, program, or lock bit configuration, or
hard-wired to VCC, depending on the application. VPEN
is treated as an input pin to enable erasing, programming, and block locking. When VPEN is lower than the
VCC lockout voltage (VLKO), all program functions are
disabled. Block erase suspend mode enables the user
to stop block erase to read data from or program data
to any other blocks. Similarly, program suspend mode
enables the user to suspend programming to read data
or execute code from any unsuspended blocks.
VPEN serves as an input with 2.7V or 3.3V for application programming. VPEN in this Q-Flash® family can
provide data protection when connected to ground.
This pin also enables program or erase lockout during
power transition.
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 3: Pin and Ball Assignment Diagrams
56-Pin TSOP Type I
A22
CE1
A21
A20
A19
A18
A17
A16
VCC
A15
A14
A13
A12
CE0
VPEN
RP#
A11
A10
A9
A8
VSS
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
64-Ball FBGA
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
WE#
OE#
STS
DQ15
DQ7
DQ14
DQ6
VSS
DQ13
DQ5
DQ12
DQ4
VCCQ
VSS
DQ11
DQ3
DQ10
DQ2
VCC
DQ9
DQ1
DQ8
DQ0
A0
BYTE#
A23
CE2
1
2
3
4
5
6
7
8
A
A1
A6
A8
VPEN
A13
VCC
A18
A22
B
A2
VSS
A9
CE0
A14
A25
A19
CE1
C
A3
A7
A10
A12
A15
DNU
A20
A21
D
A4
A5
A11
RP#
DNU
DNU
A16
A17
E
DQ8
DQ1
DQ9
DQ3
DQ4
DNU
DQ15
STS
F
BYTE#
DQ0
DQ10
DQ11
DQ12
DNU
DNU
OE#
G
A23
A0
DQ2
VCCQ
DQ5
DQ6
DQ14
WE#
H
CE2
DNU
VCC
VSS
DQ13
VSS
DQ7
NC
?Top View
(Ball? Down)
NOTE:
1. A22 only exists on the 64Mb and 128Mb devices. On the 32Mb, this pin/ball is a no connect (NC).
2. A23 only exists on the 128Mb device. On the 32Mb and 64Mb, this pin/ball is NC.
3. The # symbol indicates that the signal is active LOW.
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Part Numbering Information
Micron’s Flash devices are available with several
different combinations of features (see Figure 4).
Figure 4: Part Number Chart
MT 28F 320 J3 RG -11
Micron Technology
ET
Operating Temperature Range
ET = Extended (-40ºC to +85ºC)
Flash Family
28F = Dual-Supply
Manufacturer’s Identification Code
None = Intel (89h)
M = Micron (2Ch)
Density/Organization
XXX = x8/x16 selectable
(XXX = 320, 640, 128)
Access Time
-11 = 110ns
-115 =115ns
-12 = 120ns
Voltage/Block Organization
J3 = Smart 3 (2.70V–3.60V VCC/2.70V–3.60V)
Even sectored, compatible with Intel StrataFlash® “J3”
Package Code
TSOP
RG = 56-pin (standard) TSOP Type I
RP = 56-pin (lead-free) TSOP Type I
FBGA (standard)
FS = 64-ball (standard) FBGA
(8 x 8 grid, 1.00mm pitch, 10mm x 13mm)
(Compatible with Intel‘s Easy BGA package)
BS = 64-ball (lead-free) FBGA
(8 x 8 grid, 1.00mm pitch, 10mm x 13mm)
(Compatible with Intel’s Easy BGA package)
NOTE:
1. Lead-free packages are available. Contact factory for details.
Valid Part Number Combinations
Device Marking
After building the part number from the part number chart above, please go to Micron’s Part Marking
Decoder Web site at www.micron.com/partsearch to
verify that the part number is offered and valid. If the
device required is not on this list, please contact the
factory.
Due to the size of the package, the Micron standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross-referenced to the Micron part
numbers at www.micron.com/partsearch. To view the
location of the abbreviated mark on the device, please
refer to customer service note CSN-11, “Product Mark/
Label,” at www.micron.com/csn.
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 5: Functional Block Diagram
Input
Buffer
I/O
Control
Logic
Addr.
A[MAX:0]
X - Decoder/Block Erase Control
Buffer/
Latch
Power
(Current)
Control
CE0
CE1
CE2
OE#
WE#
RP#
VCC
Addr.
Counter
Command
Execution
State
Logic
Machine
DENSITY
A (MAX)
n
128Mb
A23
127
64Mb
A22
63
32Mb
A21
31
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
DQ0–DQ15
YDecoder
Y - Select Gates
Sense Amplifiers
Write/Erase-Bit
Compare and Verify
VPP
Switch/
Pump
VPEN
Write
Buffer
128KB Memory Block (n-2)
128KB Memory Block (n-1)
128KB Memory Block (n)
CE Logic
STS
128KB Memory Block (0)
128KB Memory Block (1)
128KB Memory Block (2)
Identification
Register
Status
Register
Query
Output
Buffer
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Table 1:
Pin/Ball Descriptions
56-PIN TSOP
NUMBERS
64-BALL FBGA
NUMBERS
SYMBOL
TYPE
DESCRIPTION
55
G8
WE#
Input
Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is
LOW, the cycle is either a WRITE to the command execution logic
(CEL) or to the memory array. Addresses and data are latched on
the rising edge of the WE# pulse.
14, 2, 29
B4, B8, H1
CE0, CE1,
CE2
Input
Chip Enable: Three CE pins enable the use of multiple Flash devices
in the system without requiring additional logic. The device can be
configured to use a single CE signal by tying CE1 and CE2 to
ground and then using CE0 as CE. Device selection occurs with the
first edge of CE0, CE1, or CE2 (CEx) that enables the device. Device
deselection occurs with the first edge of CEx that disables the
device (see Table 2 on page 11).
16
D4
RP#
Input
Reset/Power-Down: When LOW, RP# clears the status register, sets
the ISM to the array read mode, and places the device in deep
power-down mode. All inputs, including CEx, are “Don’t Care,”
and all outputs are High-Z. RP# must be held at VIH during all
other modes of operation.
54
F8
OE#
Input
Output Enables: Enables data ouput buffers when LOW. When
OE# is HIGH, the output buffers are disabled.
A0−A21/
(A22)
(A23)
Input
Address inputs during READ and WRITE operations.
A0 is only used in x8 mode and will be a NC in x16 mode (the input
buffer is turned off when BYTE = HIGH).
A22 (pin 1, ball A8) is only available on the 64Mb and 128Mb
devices.
A23 (pin 30, ball G1) is only available on the 128Mb device.
32, 28, 27, 26, G2, A1, B1, C1,
25, 24, 23, 22, D1, D2, A2, C2,
20, 19, 18, 17, A3, B3, C3, D3,
13, 12, 11, 10, 8, C4, A5, B5, C5,
7, 6, 5, 4, 3, 1, D7, D8, A7, B7,
30
C7, C8, A8, G1
31
F1
BYTE#
Input
BYTE# low places the device in the x8 mode. BYTE# high places the
device in the x16 mode and turns off the A0 input buffer. Address
A1 becomes the lowest order address in x16 mode.
15
A4
VPEN
Input
Necessary voltage for erasing blocks, programming data, or
configuring lock bits. Typically, VPEN is connected to VCC. When
VPEN ≤ VPENLK, this pin enables hardware write protect.
33, 35, 38, 40,
44, 46, 49, 51,
34, 36, 39, 41,
45, 47, 50, 52
F2, E2, G3, E4,
E5, G5, G6, H7,
E1, E3, F3, F4,
F5, H5, G7, E7
DQ0–
DQ15
Input/ Data I/O: Data output pins during any READ operation or data
Output input pins during a WRITE. DQ8–DQ15 are not used in byte mode
(BYTE = LOW).
53
E8
STS
Output Status: Indicates the status of the ISM. When configured in level
mode (default), STS acts as a RY/BY# pin. When configured in its
pulse mode, it can pulse to indicate program and/or erase
completion. Tie STS to VCCQ through a pull-up resistor.
43
G4
VCCQ
Supply VCCQ controls the output voltages. To obtain output voltage
compatible with system data bus voltages, connect VCCQ to the
system supply voltage.
9, 37
H3, A6
VCC
Supply Power Supply: 2.7V to 3.6V.
21, 42, 48
B2, H4, H6
VSS
Supply Ground.
1, 30, 56
A1, G1, H8
NC
—
No Connect: These may be driven or left unconnected. Pin 1 and
ball A8 are NCs on the 32Mb device. Pin 30 and ball G1 are NCs on
the 32Mb and 64Mb devices.
—
B6, C6, D5, D6,
E6, F6, F7, H2
DNU
—
Do Not Use: Must float to minimize noise.
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Memory Architecture
Table 2:
The MT28F128J3, MT28F640J3, and MT28F320J3
memory array architecture is divided into one hundred twenty-eight, sixty-four, or thirty-two 128KB
blocks, respectively (see Figure 6). The internal architecture allows greater flexibility when updating data
because individual code portions can be updated
independently of the rest of the code.
Figure 6: Memory Map
Chip-Enable Truth Table
CE2
CE1
CE0
DEVICE
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
NOTE:
For single-chip applications, CE2 and CE1 can be connected to GND.
When reading information in read array mode, the
device defaults to asynchronous page mode, thus providing a high data transfer rate for memory subsystems. In this state, data is internally read and stored
in a high-speed page buffer. A0–A2 select data in the
page buffer. Asynchronous page mode, with a page
size of four words or eight bytes, is supported with no
additional commands required and can be used to
access all blocks. Page mode can be used to access register information, but only one word is loaded into the
page buffer.
Read
Output Disable
Information can be read from any block, query,
identifier codes, or status register, regardless of the
VPEN voltage. The device automatically resets to read
array mode upon initial device power-up or after exit
from reset/power-down mode. To access other read
mode commands (READ ARRAY, READ QUERY, READ
IDENTIFIER CODES, or READ STATUS REGISTER),
these commands should be issued to the CUI. Six control pins dictate the data flow in and out of the device:
CE0, CE1, CE2, OE#, WE#, and RP#. In system designs
using multiple Q-Flash devices, CE0, CE1, and CE2
(CEx) select the memory device (see Table 2). To drive
data out of the device and onto the I/O bus, OE# must
be active and WE# must be inactive (VIH).
The device outputs are disabled with OE# at a logic
HIGH level (VIH). Output pins DQ0–DQ15 are placed
in High-Z.
Standby
CE0, CE1, and CE2 can disable the device (see
Table 2) and place it in standby mode, which substantially reduces device power consumption. DQ0–DQ15
outputs are placed in High-Z, independent of OE#. If
deselected during block erase, program, or lock bit
configuration, the ISM continues functioning and consuming active power until the operation completes.
Reset/Power-Down
RP# puts the device into the reset/power-down
mode when set to VIL.
During read, RP# LOW deselects the memory,
places output drivers in High-Z, and turns off internal
circuitry. RP# must be held LOW for a minimum of
t
PLPH. tRWH is required after return from reset mode
until initial memory access outputs are valid. After this
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
CLEAR BLOCK LOCK BITS command requires the
command and any address within the device. Set
BLOCK LOCK BITS command requires the command
and the block to be locked. The CEL does not occupy
an addressable memory location. It is written to when
the device is enabled and WE# is LOW. The address
and data needed to execute a command are latched on
the rising edge of WE# or the first edge of CEx that disables the device (see Table 2 on page 11). Standard
microprocessor write timings are used.
wake-up interval, normal operation is restored. The
command execution logic (CEL) is reset to the read
array mode and the status register is set to 80h.
During block erase, program, or lock bit configuration, RP# LOW aborts the operation. In default mode,
STS transitions LOW and remains LOW for a maximum time of tPLPH + tPHRH, until the RESET operation is complete. Any memory content changes are no
longer valid; the data may be partially corrupted after a
program or partially changed after an erase or lock bit
configuration. After RP# goes to logic HIGH (VIH), and
after tRS, another command can be written.
It is important to assert RP# during system reset.
After coming out of reset, the system expects to read
from the Flash memory. During block erase, program,
or lock bit configuration mode, automated Flash
memories provide status information when accessed.
When a CPU reset occurs with no Flash memory reset,
proper initialization may not occur because the Flash
memory may be providing status information instead
of array data. Micron Flash memories allow proper initialization following a system reset through the use of
the RP# input. RP# should be controlled by the same
RESET# signal that resets the system CPU.
Figure 7: Device Identifier Code
Memory Map
Read Query
The READ QUERY operation produces block status
information, CFI ID string, system interface information, device geometry information, and extended
query information. READ QUERY information is only
accessed by executing a single-word READ.
Read Identifier Codes
The READ IDENTIFIER CODES operation produces
the manufacturer code, device code, and the block
lock configuration codes for each block (see Figure 7).
The block lock configuration codes identify locked and
unlocked blocks.
Write
Writing commands to the CEL allows reading of
device data, query, identifier codes, and reading and
clearing of the status register. In addition, when VPEN =
VPENH, block erasure, program, and lock bit configuration can also be performed.
The BLOCK ERASE command requires suitable
command data and an address within the block. The
BYTE/WORD PROGRAM command requires the command and address of the location to be written to. The
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
NOTE:
When obtaining these identifier codes, A0 is not used in
either x8 or x16 modes. Data is always given on the
LOW byte in x16 mode (upper byte contains 00h).
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Bus Operation
All bus cycles to and from the Flash memory must
conform to the standard microprocessor bus cycles.
The local CPU reads and writes Flash memory
in-system.
Table 3:
Bus Operations
MODE
RP#
CE0, CE1,
CE21
OE#2
WE#2
ADDRESS
VPEN
DQ3
STS DEFAULT
MODE
NOTES
Read Array
VIH
Enabled
VIL
VIH
X
X
DOUT
High-Z4
Output Disable
Standby
Reset/Power-down
Mode
Read Identifier Codes
VIH
VIH
VIL
Enabled
Disabled
X
VIH
X
X
VIH
X
X
X
X
X
X
X
X
High-Z
High-Z
High-Z
X
X
VIH
Enabled
VIL
VIH
See Figure 7
X
High-Z4
8
Read Query
VIH
Enabled
VIL
VIH
See Table 7
X
High-Z4
9
Read Status (ISM off)
Read Status (ISM On)
DQ 7
DQ15–DQ8
DQ6–DQ0
Write
VIH
VIH
Enabled
Enabled
VIL
VIL
VIH
VIH
X
X
X
X
X
7, 10, 11
VIH
Enabled
VIH
VIL
X
VPENH
DOUT
High-Z
High-Z
DIN
5, 6, 7
High-Z4
NOTE:
See Table 2 on page 11 for valid CE configurations.
OE# and WE# should never be enabled simultaneously.
DQ refers to DQ0–DQ7 if BYTE# is LOW and DQ0–DQ15 if BYTE# is HIGH.
High-Z is VOH with an external pull-up resistor.
When Vpen £ Vpenlk, memory contents can be read, but not altered. Refer to the Recommended DC Electrical Characteristics table on page 43.
6. X can be VIL or VIH for control and address pins, and VPENLK or VPENH for VPEN. See DC Characteristics for VPENLK and
VPENH voltages.
7. In default mode, STS is VOL when the ISM is executing internal block erase, program, or lock bit configuration algorithms. It is VOH when the ISM is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/power-down mode.
8. See Read Identifier Codes section for read identifier code data.
9. See Read Query Mode Command section for read query data.
10. Command writes involving block erase, program, or lock bit configuration are reliably executed when VPEN = VPENH
and VCC is within specification.
11. Refer to Table 4 on page 14 for valid DIN during a WRITE operation.
1.
2.
3.
4.
5.
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13
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©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Command Definitions
CONFIGURATION operations. Device operations are
selected by writing specific commands into the CEL, as
seen in Table 4.
When the Vpen voltage is < Vpenlk, only READ
operations from the status register, query, identifier
codes, or blocks are enabled. Placing Vpenh on Vpen
enables BLOCK ERASE, PROGRAM, and LOCK BIT
Table 4:
Micron Q-Flash Memory Command Set Definitions
Note 1; notes appear on following page
COMMAND
READ ARRAY
READ IDENTIFIER
CODES
READ QUERY
READ STATUS
REGISTER
CLEAR STATUS
REGISTER
WRITE TO BUFFER
WORD/BYTE
PROGRAM
BLOCK ERASE
BLOCK ERASE/
PROGRAM SUSPEND
BLOCK ERASE/
PROGRAM RESUME
CONFIGURATION
SET BLOCK LOCK BITS
CLEAR BLOCK LOCK
BITS
PROTECTION
PROGRAM
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SCALABLE
OR BASIC
BUS
COMMAND CYCLES
REQ’D
SET2
FIRST BUS CYCLE
OPER3
ADDR4
SECOND BUS CYCLE
DATA5,
6
OPER3
ADDR4
DATA5,
6
NOTES
IA
ID
7
READ
READ
QA
X
QD
SRD
8
WRITE
WRITE
BA
PA
N
PD
9, 10, 11
12, 13
WRITE
BA
D0h
11, 12
14
SCS/BCS
SCS/BCS
1
≥2
WRITE
WRITE
X
X
FFh
90h
READ
SCS
SCS/BCS
≥2
2
WRITE
WRITE
X
X
98h
70h
SCS/BCS
1
WRITE
X
50h
SCS/BCS
SCS/BCS
>2
2
WRITE
WRITE
BA
X
SCS/BCS
SCS/BCS
2
1
WRITE
WRITE
BA
X
E8h
40h or
10h
20h
B0h
SCS/BCS
1
WRITE
X
D0h
SCS
SCS
SCS
2
2
2
WRITE
WRITE
WRITE
X
X
X
B8h
60h
60h
WRITE
WRITE
WRITE
X
BA
X
CC
01h
D0h
2
WRITE
X
C0h
WRITE
PA
PD
14
12
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Q-FLASH MEMORY
NOTE:
1. Commands other than those shown in Table 4 on page 14 are reserved for future device implementations and
should not be used.
2. The SCS is also referred to as the extended command set.
3. Bus operations are defined in Table 3 on page 13.
4. X = Any valid address within the device
BA = Address within the block
IA = Identifier code address; see Figure 7 on page 12 and Table 16 on page 23
QA = Query data base address
PA = Address of memory location to be programmed
5. ID = Data read from identifier codes
QD = Data read from query data base
SRD = Data read from status register; see Table 17 on page 24 for a description of the status register bits
PD = Data to be programmed at location PA; data is latched on the rising edge of WE#
CC = Configuration code
6. The upper byte of the data bus (DQ8–DQ15) during command WRITEs is a “Don’t Care” in x16 operation.
7. Following the READ IDENTIFIER CODES command, READ operations access manufacturer, device, and block lock
codes. See Block Status Register section for read identifier code data.
8. If the ISM is running, only DQ7 is valid; DQ15–DQ8 and DQ6–DQ0 are placed in High-Z.
9. After the WRITE-to-BUFFER command is issued, check the XSR to make sure a buffer is available for writing.
10. The number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. Count
ranges on this device for byte mode are n = 00h to n = 1Fh and for word mode, n = 0000h to n = 000Fh. The third
and consecutive bus cycles, as determined by n, are for writing data into the write buffer. The CONFIRM command
(D0h) is expected after exactly n + 1 WRITE cycles; any other command at that point in the sequence aborts the
WRITE-to-BUFFER operation. Please see Figure 9 on page 31, WRITE-to-BUFFER Flowchart, for additional information.
11. The WRITE-to-BUFFER or ERASE operation does not begin until a CONFIRM command (D0h) is issued.
12. Attempts to issue a block erase or program to a locked block will fail.
13. Either 40h or 10h is recognized by the ISM as the byte/word program setup.
14. Program suspend can be issued after either the WRITE-to-BUFFER or WORD/BYTE PROGRAM operation is initiated.
The CLEAR BLOCK LOCK BITS operation simultaneously clears all block lock bits.
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Q-FLASH MEMORY
READ ARRAY Command
Query Structure Output
The device defaults to read array mode upon initial
device power-up and after exiting reset/power-down
mode. The read configuration register defaults to
asynchronous read page mode. Until another command is written, the READ ARRAY command also
causes the device to enter read array mode. When the
ISM has started a block erase, program, or lock bit configuration, the device does not recognize the READ
ARRAY command until the ISM completes its operation, unless the ISM is suspended via an ERASE or
PROGRAM SUSPEND command. The READ ARRAY
command functions independently of the VPEN voltage.
The query “data base” enables system software to
obtain information about controlling the Flash component. The device’s CFI-compliant interface allows
the host system to access query data. Query data are
always located on the lowest-order data outputs
(DQ0–DQ7) only. The numerical offset value is the
address relative to the maximum bus width supported
by the device. On this family of devices, the query table
device starting address is a 10h, which is a word
address for x16 devices.
For a x16 organization, the first two bytes of the
query structure, “Q” and “R” in ASCII, appear on the
low byte at word addresses 10h and 11h. This CFIcompliant device outputs 00h data on upper bytes,
thus making the device output ASCII “Q” on the LOW
byte (DQ7–DQ0) and 00h on the HIGH byte (DQ15–
DQ8). At query addresses containing two or more
bytes of information, the least significant data byte is
located at the lower address, and the most significant
data byte is located at the higher address. This is summarized in Table 5. A more detailed example is provided in Table 6.
READ QUERY MODE Command
This section is related to the definition of the data
structure or “data base” returned by the CFI QUERY
command. System software should retain this structure to gain critical information such as block size,
density, x8/x16, and electrical specifications. When
this information has been obtained, the software
knows which command sets to use to enable Flash
writes or block erases, and otherwise control the Flash
component.
Table 5:
DEVICE
TYPE/MODE
Summary of Query-Structure Output as a Function of Device and Mode
QUERY START LOCATION IN
MAXIMUM DEVICE BUS WIDTH
ADDRESSES
x16 device
x16 mode
x16 device
x8 mode
10h
QUERY DATA WITH MAXIMUM
DEVICE BUS WIDTH
ADDRESSING
QUERY DATA WITH BYTE
ADDRESSING
HEX
OFFSET
HEX
CODE
ASCII
VALUE
HEX
OFFSET
HEX
CODE
ASCII
VALUE
10
11
12
0051
0052
0059
Q
R
Y
20
21
22
20
21
22
51
00
52
51
51
52
Q
Null
R
Q
Q
R
N/A1
N/A1
NOTE:
1. The system must drive the lowest-order addresses to access all the device’s array data when the device is configured
in x8 mode. Therefore, word addressing where these lower addresses are not toggled by the system is “Not Applicable” for x8-configured devices.
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Q-FLASH MEMORY
Query Structure Overview
The QUERY command makes the Flash component
display the CFI query structure or data base. The structure subsections and address locations are outlined in
Table 7.
Table 6:
Example: Query Structure Output of x16- and x8-Capable Devices
WORD ADDRESSING
1
OFFSET
BYTE ADDRESSING
HEX CODE
A16–A1
VALUE
OFFSET
DQ15–DQ0
0010h
0011h
0012h
0013h
0014h
0015h
0016h
0017h
0018h
...
0051
0052
0059
P_ID LO
P_ID HI
P LO
P HI
A_ID LO
A_ID HI
...
HEX CODE
A7–A0
Q
R
Y
PrVendor
ID#
PrVendor
TblAdr
AltVendor
ID#
...
20h
21h
22h
23h
24h
25h
26h
27h
28h
...
VALUE
DQ7–DQ0
51
51
52
52
59
59
P_ID LO
P_ID LO
P_ID HI
...
Q
Q
R
R
Y
Y
PrVendor
PrVendor
ID#
...
NOTE:
1. In word mode, A0 is not driven, so 0010h means that Address A5 = 1.
Table 7:
Query Structure1
OFFSET
SUBSECTION NAME
DESCRIPTION
Block Status Register
Manufacturer compatibility code
Device code
Block-specific information
00h
01h
(BA+2)h2
03–0Fh
10h
1Bh
27h
P3
Reserved
CFI Query Identification String
System Interface Information
Device Geometry Definition
Primary Extended Query Table
Reserved for vendor-specific information
Reserved for vendor-specific information
Command-set ID and vendor data offset
Flash device layout
Vendor-defined additional information specific to the primary
vendor algorithm
NOTE:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode.
2. BA = Block address beginning location (i.e., 020000h is block two’s beginning location when the block size is 64Kword).
3. Offset 15 defines “P,” which points to the Primary Extended Query Table.
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128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
CFI Query Identification String
The CFI query identification string verifies whether
the component supports the CFI specification. Additionally, it indicates the specification version and supported vendor-specified command set(s).
Table 8:
Block Status Register
OFFSET
LENGTH
(BA+2)h1
1
ADDRESS1
DESCRIPTION
VALUE
(BA+2)h
Block Lock Status Register
BSR0 Block Lock Status
0 = Unlocked
1 = Locked
BSR1–7 Reserved for Future Use
(BA+2)h
(Bit 0) 0 or 1
(BA+2)h
(Bit 1–7) 0
NOTE:
1. BA = the beginning location of a block address (i.e., 010000h is block one’s [64K-word] beginning location in word
mode).
Table 9:
OFFSET
CFI Identification
LENGTH DESCRIPTION
10h
3
Query-unique ASCII string “QRY”
13h
2
15h
2
Primary vendor command set and control interface ID code. 16bit ID code for vendor-specified algorithms
Extended query table primary algorithm
17h
2
19h
2
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Alternate vendor command set and control interface ID code;
0000h means no second vendor-specified algorithm exists
Secondary algorithm extended query table address; 0000h
means none exists
18
ADDRESS
HEX
CODE
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
51
52
59
01
00
31
00
00
00
00
00
VALUE
Q
R
Y
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Q-FLASH MEMORY
System Interface Information
Table 10 provides useful information about optimizing system interface software.
Table 10: System Interface Information
OFFSET
LENGTH DESCRIPTION
ADDRESS
HEX
CODE
VALUE
1Bh
27
2.7V
1Ch
36
3.6V
1Dh
00
0.0V
1Eh
00
0.0V
1Fh
07
128µs
20h
07
128µs
21h
0A
1s
1Bh
1
1Ch
1
1Dh
1
1Eh
1
1Fh
1
20h
1
21h
1
“n” such that typical block erase timeout =
22h
1
“n” such that typical full chip erase timeout = 2nms
22h
00
N/A
23h
1
“n” such that word program timeout = 2n times typical
23h
04
2ms
24h
1
“n” such that typical max. buffer write timeout = 2n times
typical
24h
04
2ms
25h
1
“n” such that maximum block erase timeout = 2n times typical
25h
04
16s
26h
1
“n” such that maximum chip erase timeout = 2n times typical
26h
00
N/A
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VCC logic supply minimum program/erase voltage
Bits 0–3 BCD 100mV
Bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
Bits 0–3 BCD 100mV
Bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
Bits 0–3 BCD 100mV
Bits 4–7 Hex volts
VPP [programming] supply maximum program/erase voltage
Bits 0–3 BCD 100mV
Bits 4–7 Hex volts
“n” such that typical single word program timeout = 2nµs
“n” such that typical max. buffer write timeout =
19
2nms
2nµs
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Q-FLASH MEMORY
Device Geometry Definition
Tables 11 and 12 provide important details about
the device geometry.
Table 11: Device Geometry Definitions
OFFSET
LENGTH
27h
1
28h
2
2Ah
2
2Ch
1
2Dh
4
CODE
(see table 12 below)
DESCRIPTION
“n” such that device size= 2n in number of bytes
Flash device interface: x8 async, x16 async, x8/x16 async; 28:00
29:00, 28:01 29:00, 28:02 29:00
“n” such that maximum number of bytes in write buffer = 2n
Number of erase block regions within device:
1. x = 0 means no erase blocking; the device erases in “bulk”
2. x specifies the number of device or partition regions with
one or more contiguous same-size erase blocks
3. Symmetrically blocked partitions have one blocking region
4. Partition size = (total blocks) x (individual block size)
Erase Block Region 1 Information
Bits 0–15 = y; y + 1 = number of identical-size erase blocks
Bits 16–31 = z; region erase block(s) size are z x 256 bytes
27h
28h
29h
2Ah
2Bh
2Ch
02
00
05
00
01
x8/x16
32
1
2Dh
2Eh
2Fh
30h
Table 12: Device Geometry Definition Codes
ADDRESS
32Mb
64Mb
128Mb
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
16
02
00
05
00
01
1F
00
00
02
17
02
00
05
00
01
3F
00
00
02
18
02
00
05
00
01
7F
00
00
02
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Q-FLASH MEMORY
Primary Vendor-Specific ExtendedQuery Table
Table 13 includes information about optional Flash
features and commands and other similar information.
Table 13: Primary Vendor-Specific Extended-Query
OFFSET1 DESCRIPTION
P = 31h (OPTIONAL FLASH FEATURES AND COMMANDS)
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
(P+9)h
(P+A)h
(P+B)h
(P+C)h
(P+D)h
Primary extended query table
Unique ASCII string, PRI
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1 = yes, 0 = no) bits 9–31are
reserved; undefined bits are “0.” If bit 31 is “1,” then another 31-bit field
of optional features follows at the end of the bit 30 field.
Bit 0 Chip erase supported = no = 0
Bit 1 Suspend erase supported = yes = 1
Bit 2 Suspend program supported = yes = 1
Bit 3 Legacy lock/unlock supported = no = 0
Bit 4 Queued erase supported = no = 0
Bit 5 Instant Individual block locking supported = no = 0
Bit 6 Protection bits supported = yes = 1
Bit 7 Page mode read supported = yes = 1
Supported functions after suspend: read array, status, query
Other supported operations:
Bits 1–7 Reserved; undefined bits are “0”
Bit 0 Program supported after erase suspend = yes = 1
Block status register mask
Bits 2–15 Reserved; undefined bits are “0”
Bit 0 Block lock bit status register active = yes = 1
Bit 1 Block lock down bit status active = no = 0
VCC logic supply highest-performance program/erase voltage
Bits 0–3 BCD value in 100mV
Bits 4–7 BCD value in volts
VPP optimum program/erase supply voltage
Bits 0–3 BCD value in 100mV
Bits 4–7 Hex value in volts
ADDRESS
HEX
CODE
31h
32h
33h
34h
35h
36h
37h
38h
39h
50
52
49
31
31
C6h
00
00
00
3Ah
01
3Bh
3Ch
01
00
3Dh
33
3.3V
3Eh
00
0.0V
VALUE
P
R
I
1
1
NOTE:
1. The variable “P” is a pointer which is defined at CFI offset 15h.
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Q-FLASH MEMORY
Table 14: Protection Register Information
OFFSET1 DESCRIPTION
P = 31h (Optional Flash Features and Commands)
(P+E)h
(P+F)h
(P+10)h
(P+11)h
(P+12)h
Number of protection register fields in JEDEC ID space. “00h” indicates
that 256 protection bytes are available.
Protection Field 1: Protection Description
This field describes user-available, one-time programmable (OTP)
protection register bytes. Some are pre-programmed with device-unique
serial numbers; others are user-programmable. Bits 0–15 point to the
protection register lock byte, the section’s first byte.
The following bytes are factory-pre-programmed and user-programmable.
Bits 0–7 Lock/bytes JEDEC-plane physical low address
Bits 8–15 Lock/bytes JEDEC-plane physical high address
Bits 16–23 “n” such that 2n = factory pre-programmed bytes
Bits 24–31 “n” such that 2n = user-programmable bytes
ADDRESS
HEX
VALUE
CODE
3Fh
01
01
40h
00
00h
ADDRESS
HEX
VALUE
CODE
44h
03
8 byte
45h
00
NOTE:
1. The variable “P” is a pointer which is defined at CFI offset 15h.
Table 15: Burst READ Information
OFFSET1 DESCRIPTION
P = 31h (Optional Flash Features and Commands)
(P+13)h
(P+14)h
(P+15)h
Page Mode Read Capability
Bits 0–7 = “n” such that 2n Hex value represents the number of read page
bytes. See offset 28h for device word width to determine page mode data
output width. 00h indicates no read page buffer.
Number of synchronous mode read configuration fields that follow. 00h
indicates no burst capability.
Reserved for future use.
46h
NOTE:
1. The variable “P” is a pointer which is defined at CFI offset 15h.
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Q-FLASH MEMORY
READ IDENTIFIER CODES Command
device is in this mode, all subsequent READ operations output data from the status register until another
valid command is written. Page mode READs are not
supported in this read mode.
The status register contents are latched on the falling edge of OE# or the first edge of CEx that enables the
device (see Table 2 on page 11). To update the status
register latch, OE# must toggle to VIH or the device
must be disabled before further READs. The READ
STATUS REGISTER command functions independently of the VPEN voltage. During a program, block
erase, set block lock bits, or clear block lock bits command sequence, only SR7 is valid until the ISM completes or suspends the operation. Device I/O pins
DQ0–DQ6 and DQ8–DQ15 are placed in High-Z. When
the operation completes or suspends (check status
register bit 7), all contents of the status register are
valid during a READ.
Writing the READ IDENTIFIER CODES command
initiates the IDENTIFIER CODE operation. Following
the writing of the command, READ cycles from
addresses shown in Figure 7 on page 12 retrieve the
manufacturer, device, and block lock configuration
codes (see Table 16 on page 23 for identifier code values). Page mode READs are not supported in this read
mode. To terminate the operation, write another valid
command. The READ IDENTIFIER CODES command
functions independently of the VPEN voltage. This
command is valid only when the ISM is off or the
device is suspended. See Table 16 on page 23 for read
identifier codes.
READ STATUS REGISTER Command
The status register may be read one of two ways:
either issue a discrete READ STATUS REGISTER command or when the ISM is running, a READ of the
device will provide valid status register data. Once the
Table 16: Identifier Codes
ADDRESS1
CODE
Manufacturer’s Identification Code2
• Intel ManID
• Micron ManID
Device Code
• 32Mb
• 64Mb
• 128Mb
Block Lock Configuration
• Block is Unlocked
• Block is Locked
• Reserved for Future Use
X00000h
X00001h
XX0002h3
DATA
(00) 89
(00) 2C
(00) 16
(00) 17
(00) 18
DQ0 = 0
DQ0 = 1
DQ1–DQ7
NOTE:
1. A0 is not used in either x8 or x16 modes when obtaining the identifier codes. The lowest-order address line is A1.
Data is always presented on the low byte in x16 mode (upper byte contains 00h).
2. Different ManID devices are ordered via separate part numbers. See Figure 4 on page 8 for details.
3. X selects the specific block’s lock configuration code. See Figure 6 on page 11 for the device identifier code memory
map.
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Q-FLASH MEMORY
Table 17: Status Register Definitions
ISMS
ESS
ECLBS
PSLBS
VPENS
PSS
DPS
R
7
6
5
4
3
2
1
0
HIGH-Z
WHEN
BUSY?
STATUS REGISTER BITS
NOTES
No
SR7 = WRITE STATE MACHINE STATUS (ISMS)
1 = Ready
0 = Busy
Yes
SR6 = ERASE SUSPEND STATUS (ESS)
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR5 = ERASE AND CLEAR LOCK BITS STATUS (ECLBS)
1 = Error in Block Erasure or Clear Block Bits
0 = Successful Block Erase or Clear Lock Bits
SR4 = PROGRAM AND SET LOCK BIT STATUS (PSLBS)
1 = Error in Programming or Setting Block Lock Bits
0 = Successful Program or Set Block Lock Bits
SR3 = PROGRAMMING VOLTAGE STATUS (VPENS)
1 = Low Programming Voltage Detected,
Operation Aborted
0 = Programming Voltage OK
Yes
Yes
Yes
Yes
Yes
Yes
Check STS or SR7 to determine block erase,
program, or lock bit configuration
completion. SR6–SR0 are not driven while
SR7 = 0.
SR2 = PROGRAM SUSPEND STATUS (PSS)
1 = Program Suspended
0 = Program in Progress/Completed
SR1 DEVICE PROTECTSTATUS (DPS)
1 = Block Lock Bit Detected, Operation Aborted
0 = Unlock
If both SR5 and SR4 are “1s” after a block
erase, program, writer buffer command, or
lock bit configuration attempt, an improper
command sequence was entered.
SR3 does not provide a continuous voltage
level indication. The ISM interrogates and
indicates the programming voltage level
only after block erase, program, set block
lock bits, or clear block lock bits command
sequences.
SR1 does not provide a continuous
indication of block lock bit values. The ISM
interrogates the block lock bits only after
block erase, program, or lock bit
configuration command sequences. It
informs the system, depending on the
attempted operation, if the block lock bit is
set. Read the block lock configuration codes
using the READ IDENTIFIER CODES command
to determine block lock bits status. SR0 is
reserved for future use and should be
masked when polling the status register.
SR0 = RESERVED FOR FUTURE ENHANCEMENTS
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
CLEAR STATUS REGISTER Command
BLOCK ERASE SUSPEND Command
The ISM sets the status register bits SR5, SR4, SR3,
and SR1 to “1s.” These bits, which indicate various failure conditions, can only be reset by the CLEAR STATUS REGISTER command. Allowing system software
to reset these bits can perform several operations
(such as cumulatively erasing or locking multiple
blocks or writing several bytes in sequence). To determine if an error occurred during the sequence, the status register may be polled. To clear the status register,
the CLEAR STATUS REGISTER command (50h) is written. The CLEAR STATUS REGISTER command functions independently of the applied VPEN voltage and is
only valid when the ISM is off or the device is suspended.
The BLOCK ERASE SUSPEND command allows
block erase interruption in order to read or program
data in another block of memory. Writing the BLOCK
ERASE SUSPEND command immediately after starting
the block erase process requests that the ISM suspend
the block erase sequence at an appropriate point in
the algorithm. When reading after the BLOCK ERASE
SUSPEND command is written, the device outputs status register data. Polling status register bit SR7, followed by SR6, shows when the BLOCK ERASE
operation has been suspended. In the default mode,
STS also transitions to VOH. tLES defines the block
erase suspend latency. At this point, a READ ARRAY
command can be written to read data from blocks
other than that which is suspended. During erase suspend to program data in other blocks, a program command sequence can also be issued. During a
PROGRAM operation with block erase suspended, status register bit SR7 returns to “0” and STS output (in
default mode) transitions to VOL. However, SR6
remains “1” to indicate block erase suspend status.
Using the PROGRAM SUSPEND command, a program
operation can also be suspended. Resuming a SUSPENDED programming operation by issuing the Program Resume command enables the suspended
programming operation to continue. To resume the
suspended erase, the user must wait for the programming operation to complete before issuing the Block
ERASE RESUME command. While block erase is suspended, the only other valid commands are READ
QUERY, READ STATUS REGISTER, CLEAR STATUS
REGISTER, CONFIGURE, and BLOCK ERASE
RESUME. After a BLOCK ERASE RESUME command to
the Flash memory is completed, the ISM continues the
block erase process. Status register bits SR6 and SR7
automatically clear and STS (in default mode) returns
to VOL. After the ERASE RESUME command is completed, the device automatically outputs status register
data when read. VPEN must remain at VPENH (the same
VPEN level used for block erase) during block erase suspension. Block erase cannot resume during block
erase suspend until PROGRAM operations are complete.
BLOCK ERASE Command
The BLOCK ERASE command is a two-cycle command that erases one block. First, a block erase setup
is written, followed by a block erase confirm. This
command sequence requires an appropriate address
within the block to be erased. The ISM handles all
block preconditioning, erase, and verify. Time tWB
after the two-cycle block erase sequence is written, the
device automatically outputs status register data when
read. The CPU can detect block erase completion by
analyzing the output of the STS pin or status register
bit SR7. Toggle OE# or CEx to update the status register. Upon block erase completion, status register bit
SR5 should be checked to detect any block erase error.
When an error is detected, the status register should be
cleared before system software attempts corrective
actions. The CEL remains in read status register mode
until a new command is issued. This two-step setup
command sequence ensures that block contents are
not accidentally erased. An invalid block erase command sequence results in status register bits SR4 and
SR5 being set to “1.” Also, reliable block erasure can
only occur when VCC is valid and VPEN = VPENH. Note
that SR3 and SR5 are set to “1” if block erase is
attempted while VPEN ≤ VPENLK. Successful block erase
requires that the corresponding block lock bit be
cleared. Similarly, SR1 and SR5 are set to “1” if block
erase is attempted when the corresponding block lock
bit is set.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
WRITE-to-BUFFER Command
the device receives a command other than WRITE
CONFIRM, an invalid command/sequence error is
generated and status register bits SR5 and SR4 are set
to “1.” For additional BUFFER WRITEs, issue another
WRITE-to-BUFFER SETUP command and check XSR7.
If an error occurs during a write, the device stops
writing, and status register bit SR4 is set to a “1” to
indicate a program failure. The ISM only detects errors
for “1s” that do not successfully program to “0s.” When
a program error is detected, the status register should
be cleared. Note that the device does not accept any
more WRITE-to-BUFFER commands any time SR4
and/or SR5 is set. In addition, if the user attempts to
program past an erase block boundary with a WRITEto-BUFFER command, the device aborts the WRITEto-BUFFER operation and generates an invalid command/sequence error, and status register bits SR5 and
SR4 are set to “1.”
Reliable BUFFERED WRITEs can only occur when
VPEN = VPENH. If a BUFFERED WRITE is attempted
while VPEN ≤ VPENLK, status register bits SR4 and SR3
are set to “1.” Buffered write attempts with invalid VCC
and VPEN voltages produce spurious results and
should not be attempted. Finally, the corresponding
block lock bit should be reset for successful programming. When a BUFFERED WRITE is attempted while
the corresponding block lock bit is set, SR1 and SR4 are
set to “1.”
The write-to-buffer command sequence is initiated
to program the Flash device via the write buffer. A
buffer can be loaded with a variable number of bytes,
up to the buffer size, before writing to the Flash device.
First, the WRITE-to-BUFFER SETUP command is
issued, along with the block address (see Figure 9 on
page 31). Then, the extended status register (XSR; see
Table 18) information is loaded and XSR7 indicates
“buffer available” status. If XSR7 = 0, the write buffer is
not available. To retry, issue the Write-to-Buffer setup
command with the block address and continue monitoring XSR7 until XSR7 = 1. When XSR7 transitions to
“1,” the buffer is ready for loading new data. Then the
part is given a word/byte count with the block address.
On the next write, a device start address is given, along
with the write buffer data. Depending on the count,
subsequent writes provide additional device addresses
and data. All subsequent addresses must lie within the
start address plus the count.
The device internally programs many Flash cells in
parallel. Due to this parallel programming, maximum
programming performance and lower power are
obtained by aligning the start address at the beginning
of a write buffer boundary (i.e., A0–A4 of the start
address = 0).
When the final buffer data is given, a WRITE CONFIRM command is issued, thus programming the ISM
to begin copying the buffer data to the Flash array. If
Table 18: Extended Status Register Definitions (XSR)
WBS
RESERVED
7
6–0
HIGH-Z WHEN
BUSY?
No
Yes
STATUS REGISTER BITS
NOTES
XSR7 = WRITE BUFFER STATUS (WBS)
1 = Write Buffer Available
0 = Write Buffer Not Available
XSR6–XSR0 = RESERVED FOR FUTURE ENHANCEMENTS
After a BUFFER WRITE command, ZXSR7 = 1
indicates that a write buffer is available.
SR6–SR0 are reserved for future use and
should be masked when polling the status
register.
NOTE:
To access the XSR data, issue only a READ to the device.
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©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
BYTE/WORD PROGRAM Commands
automatically outputs status register data when read.
VPEN must remain at VPENH and VCC must remain at
valid VCC levels (the same VPEN and VCC levels used for
programming) while in program suspend mode. Refer
to Figure 11 on page 33 (PROGRAM SUSPEND/
RESUME Flowchart).
A two-cycle command sequence executes a byte/
word program setup. This program setup (standard
40h or alternate 10h) is written, followed by a second
write that specifies the address and data (latched on
the rising edge of WE#). Next, the ISM takes over to
internally control the programming and program verify algorithms. When the program sequence is written,
the device automatically outputs status register data
when read (see Figure 10 on page 32). The CPU can
detect the completion of the program event by analyzing the STS pin or status register bit SR7.
Upon program completion, status register bit SR4
should be checked. The status register should be
cleared if a program error is detected. The ISM only
detects errors for “1s” that do not successfully program
to “0s.” The CEL remains in read status register mode
until it receives another command.
Reliable byte/word programs can only occur when
VCC and VPEN are valid. Status register bits SR4 and
SR3 are set to “1” if a byte/word program is attempted
while VPEN ≤ VPENLK. The corresponding block lock bit
should be cleared for successful byte/word programs.
If BYTE/WORD is attempted while the corresponding
block lock bit is set, SR1 and SR4 are set to “1.”
SET READ CONFIGURATION Command
Q-Flash memory does not support the SET READ
CONFIGURATION command. The devices default to
the asynchronous page mode. If this command is
given, the operation of the device will not be affected.
READ Configuration
Micron’s Q-Flash devices support both asynchronous page mode and standard word/byte READs without configuration requirement. Status register and
identifier only support standard word/byte single
READ operations.
STS CONFIGURATION Command
Using the CONFIGURATION command, the STS
pin can be configured to different states. Once configured, the STS pin remains in that configuration until
another configuration command is issued, RP# is
asserted low, or the device is powered down. Initially,
the STS pin defaults to RY/BY# operation where RY/
BY# goes LOW to indicate that the state machine is
busy. When HIGH, RY/BY# indicates that either the
state machine is ready for a new operation or it is suspended. Table 19 on page 28, Configuration Coding
Definitions, shows the possible STS configurations. To
change the STS pin to other modes, the CONFIGURATION command is given, followed by the desired configuration code. The three alternate configurations are
all pulse modes and may be used as a system interrupt.
With these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 controls program complete interrupt pulse. Providing the 00h configuration
code with the CONFIGURATION command resets the
STS pin to the default RY/BY# level mode. Table 19 on
page 28 describes possible configurations and usage.
The CONFIGURATION command can only be given
when the device is not busy or suspended. When configured in one of the pulse modes, the STS pin pulses
LOW with a typical pulse width of 250ns. Check SR7 for
device status. An invalid configuration code results in
status register bits SR4 and SR5 being set to “1.”
PROGRAM SUSPEND Command
The PROGRAM SUSPEND command enables program interruption to read data in other Flash memory
locations. After starting the programming process,
writing the PROGRAM SUSPEND command requests
that the ISM suspend the program sequence at a predetermined point in the algorithm. When the PROGRAM SUSPEND command is written, the device
continues to output status register data when read.
Polling status register bit SR7 can determine when the
programming operation has been suspended. When
SR7 = 1, SR2 is also set to “1” to indicate that the device
is in the program suspend mode. STS in RY/BY# level
mode also transitions to VOH. Note that tLPS defines
the program suspend latency.
Hence, a READ ARRAY command can be written to
read data from unsuspended locations. While programming is suspended, the only other valid commands are READ QUERY, READ STATUS REGISTER,
CLEAR STATUS REGISTER, CONFIGURE, and PROGRAM RESUME. When the PROGRAM RESUME command is written, the ISM continues the programming
process. Status register bits SR2 and SR7 automatically
clear and STS in RY/BY# mode returns to VOL. After the
PROGRAM RESUME command is written, the device
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Table 19: Configuration Coding Definitions1
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
RESERVED
DQ1–DQ0 = STS Configuration Codes
00 = Default, RY/BY# level mode (device
ready) indication
01 = Pulse on Erase Complete
10 = Pulse on Program Complete
11 = Pulse on Erase or Program Complete
DQ1
DQ0
PULSE ON
PROGRAM
COMPLETE2
PULSE ON
ERASE
COMPLETE2
NOTES
Used to control HOLD to a memory controller to prevent accessing a Flash
memory subsystem while any Flash device’s ISM is busy.
Used to generate a system interrupt pulse when any Flash device is an array
has completed a BLOCK ERASE or sequence of queued BLOCK ERASEs;
helpful for reformatting blocks after file system free space reclamation or
“clean-up.”
Used to generate a system interrupt pulse when any Flash device in an array
has completed a PROGRAM operation. Provides highest performance for
enabling continuous BUFFER WRITE operations.
Used to generate system interrupts to trigger enabling of Flash arrays when
either ERASE or PROGRAM operations are completed and a common
interrupt service routine is desired.
NOTE:
1. An invalid configuration code will result in both SR4 and SR5 being set.
2. When the device is configured in one of the pulse modes, the STS pin pulses LOW with a typical pulse width of
250ns.
SET BLOCK LOCK BITS Command
CLEAR BLOCK LOCK BITS Command
A flexible block locking and unlocking scheme is
enabled via a combination of block lock bits. The block
lock bits gate PROGRAM and ERASE operations. Using
the SET BLOCK LOCK BITS command, individual
block lock bits can be set. This command is invalid
when the ISM is running or when the device is suspended. SET BLOCK LOCK BITS commands are executed by a two-cycle sequence. The set block lock bits
setup, along with appropriate block address, is followed by the set block lock bits confirm and an
address within the block to be locked. The ISM then
controls the set lock bit algorithm. When the sequence
is written, the device automatically outputs status register data when read (see Figure 14 on page 36). The
CPU can detect the completion of the set block lock bit
event by analyzing the STS pin output or status register
bit SR7. Upon completion of set block lock bits operation, status register bit SR4 should be checked for
error. If an error is detected, the status register should
be cleared. The CEL remains in read status register
mode until a new command is issued. This two-step
sequence of setup followed by execution ensures that
lock bits are not accidentally set. An invalid SET
BLOCK LOCK BITS command results in status register
bits SR4 and SR5 being set to “1.”
The CLEAR BLOCK LOCK BITS command can clear
all set block lock bits in parallel. This command is
invalid when the ISM is running or the device is suspended. The CLEAR BLOCK LOCK BITS command is
executed by a two-cycle sequence. First, a clear block
lock bits setup is written, followed by a CLEAR BLOCK
LOCK BITS CONFIRM command. Then the device
automatically outputs status register data when read
(see Figure 14 on page 36). The CPU can detect completion of the clear block lock bits event by analyzing
the STS pin output or the status register bit SR7. When
the operation is completed, status register bit SR5
should be checked. If a clear block lock bits error is
detected, the status register should be cleared. The
CEL remains in read status register mode until another
command is issued.
This two-step setup sequence ensures that block
lock bits are not accidentally cleared. An invalid
CLEAR BLOCK LOCK BITS command sequence results
in status register bits SR4 and SR5 being set to “1.”
Also, a reliable CLEAR BLOCK LOCK BITS operation
can only occur when VCC and VPEN are valid. If a clear
block lock bits operation is attempted when VPEN ≤
VPENLK, SR3 and SR5 are set to “1.” If a CLEAR BLOCK
LOCK BITS operation is aborted due to VPEN or VCC
transitioning out of valid range, block lock bit values
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
bit SR4 is set to “1”). Attempting to program a locked
protection register segment results in a status register
error (program error bit SR4 and lock error bit SR1 are
set to “1”).
are left in an undetermined state. To initialize block
lock bit contents to known values, a repeat of CLEAR
BLOCK LOCK BITS is required.
PROTECTION REGISTER PROGRAM
Command
Locking the Protection Register
The 3V Q-Flash memory includes a 128-bit protection register to increase the security of a system
design. For example, the number contained in the protection register can be used for the Flash component
to communicate with other system components, such
as the CPU or ASIC, to prevent device substitution. The
128 bits of the protection register are divided into two
64-bit segments. One of the segments is programmed
at the Micron factory with a unique and unchangeable
64-bit number. The other segment is left blank for customers to program as needed. After the customer segment is programmed, it can be locked to prevent
reprogramming.
By programming bit 1 of the PR-LOCK location to
“0,” the user-programmable segment of the protection
register is lockable. To protect the unique device number, bit 0 of this location is programmed to “0” at the
Micron factory. Bit 1 is set using the PROTECTION
PROGRAM command to program “FFFDh” to the PRLOCK location. When these bits have been programmed, no further changes can be made to the values stored in the protection register. PROTECTION
PROGRAM commands to a locked section will result in
a status register error (program error bit SR4 and lock
error bit SR1 are set to “1”). Note that the protection
register lockout state is not reversible.
Figure 8: Protection Register Memory
Map
Reading the Protection Register
The protection register is read in the identification
read mode. The device is switched to identification
read mode by writing the READ IDENTIFIER command (90h). When in this mode, READ cycles from
addresses shown in Table 20 on page 30 or Table 21 on
page 30 retrieve the specified information. To return to
read array mode, the READ ARRAY command (FFh)
must be written.
Word
Address
88h
4 Words
User-Programmed
85h
84h
Programming the Protection Register
4 Words
Factory-Programmed
The protection register bits are programmed with
two-cycle PROTECTION PROGRAM commands.
The 64-bit number is programmed 16 bits at a time
for word-wide parts and eight bits at a time for bytewide parts. First, the PROTECTION PROGRAM SETUP
command, C0h, is written. The next write to the device
latches in addresses and data, and programs the specified location. The allowable addresses are shown in
Table 20 on page 30 and Table 21 on page 30. Any
attempt to address PROTECTION PROGRAM commands outside the defined protection register address
space results in a status register error (program error
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81h
80h
1 Word Lock
0
NOTE:
A0 is not used in x16 mode when accessing the protection register map (see Table 20 on page 30 for x16
addressing). A0 is used for x8 mode (see Table 21 on
page 30 for x8 addressing).
29
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©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Table 20: Word-Wide Protection Register Addressing
WORD
USE
A8
A7
A6
A5
A4
A3
A2
A1
LOCK
0
1
2
3
4
5
6
7
Both
Factory
Factory
Factory
Factory
User
User
User
User
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Table 21: Byte-Wide Protection Register Addressing
BYTE
LOCK
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
USE
A8
A7
A6
A5
A4
A3
A2
A1
A0
Both
Factory
Factory
Factory
Factory
Factory
Factory
Factory
Factory
User
User
User
User
User
User
User
User
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NOTE:
All address lines not specified in the above tables must be “0”when accessing the protection register (i.e., A24–A9 = 0).
09005aef80b5a323
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©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 9: WRITE-to-BUFFER Flowchart
BUS
OPERATION COMMAND COMMENTS
Start
Set Timeout
WRITE
Issue
WRITE-to-BUFFER
Command E8h,
Block Address
No
Read Extended
Status Register
XSR7 =
0
WRITE-toBUFFER
READ
XSR7 = Valid
Addr = Block Address
STANDBY
Check XSR7
1 = Write Buffer Available
0 = Write Buffer Not
Available
WRITE
Data = N = Word/Byte
Count
N = 0 Corresponds to Count
=1
Addr = Block Address
2, 3
WRITE
Data = Write Buffer Data
Addr = Device Start
Address
4, 5
WRITE
Data = Write Buffer Data
Addr = Device Address
6, 7
WRITE-toBUFFER Timeout?
1
Write Word or
Byte Count N,
Block Address
Write Buffer Data,
Start Address
X=0
Yes
Check
X = N?
No
Yes
Abort
Yes
WRITE-to-BUFFER
Command?
Yes
WRITE
Write to Another
Block Address
No
Write to Buffer
Aborted
Write Next Buffer
Data, Device Address
Yes
Another
WRITE-to-BUFFER
?
Issue
READ STATUS
Command
No
1
Data = D0h
Addr = Block Address
Status register data with
the device enabled, OE#
LOW updates the SR
Addr = Block Address
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
8
Full status check can be done after all erase and write sequences
complete. Write FFh after the last operation to reset the device
to read array mode.
Read Status Register
1
SR7 =
Program
Buffer to
Flash
Confirm
READ
X=X+1
Program Buffer to
Flash Confirm D0h
NOTES
Data = E8h
Block Address
0
1
Full Status
Check if Desired
Programming
Complete
NOTE:
1. Issuing a READ STATUS REGISTER command (70h) will result in an invalid WRITE BUFFER command.
2. Byte or word count values on DQ0–DQ7 are loaded into the count register. Count ranges on this device for byte
mode are n = 00h to 1Fh and for word mode are n = 0000h to 000Fh.
3. The device now outputs the status register when read (XSR is no longer available).
4. Write buffer contents will be programmed at the device start address or destination Flash address.
5. Align the start address on a write buffer boundary for maximum programming performance (i.e., A4–A0 of the
start address = 0).
6. The device aborts the WRITE-to-BUFFER command if the current address is outside of the original block address.
7. The status register indicates an “improper command sequence” if the WRITE-to-BUFFER command is aborted. Follow this with a CLEAR STATUS REGISTER command.
8. Toggling OE# (LOW to HIGH to LOW) updates the status register. This must be done in place of issuing the READ
STATUS REGISTER command.
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©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 10: BYTE/WORD PROGRAM
Flowchart
BUS
OPERATION
Start
Write 40h,
Address
COMMAND
COMMENTS
WRITE
SETUP BYTE/
WORD
PROGRAM
Data = 40h
Addr = Location to be
programmed
WRITE
BYTE/WORD
PROGRAM
Data = Data to be
programmed
Addr = Location to be
programmed
Write Data and
Address
Read Status
Register
READ
Status Register Data
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
Toggling OE# (LOW to HIGH to LOW) updates the status register.
To ensure the availability of correct status, please follow the
timings shown in Figure 20 on page 50. This can be done in
place of issuing the READ STATUS REGISTER command. Repeat
for subsequent programming operations.
0
SR7 =
1
Full Status
Check if Desired
After each program operation or after a sequence of
programming operations, an SR full status check can be done.
Byte/Word
Program Complete
Write FFh after the last program operation to place the device in
read array mode.
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (see above)
BUS
OPERATION
1
SR3 =
COMMAND
COMMENTS
WRITE
SETUP BYTE/
WORD
PROGRAM
Check SR3
1 = Programming to
Voltage Error Detect
WRITE
BYTE/WORD
PROGRAM
Check SR1
1 = Device Protect Detect
RP# = VIH, Block Lock Bit is
Set
Only required for systems
implementing lock bit
configuration
Voltage Range Error
0
1
Device Protect Error
SR1 =
0
1
SR4 =
Programming Error
0
READ
Status Register Data
STANDBY
Check SR4
1 = Programming Error
Toggling OE# (LOW to HIGH to LOW) updates the status register.
This can be done in place of issuing the READ STATUS REGISTER
command. Repeat for subsequent programming operations.
Byte/Word
Program Successful
SR4, SR3, and SR1 are only cleared by the Clear Status Register
command in cases where multiple locations are programmed
before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 11: PROGRAM SUSPEND/RESUME
Flowchart
Start
Write B0h
Read Status
Register
BUS OPERATION
COMMAND
COMMENTS
WRITE
PROGRAM
SUSPEND
Data = B0h
Addr = X
READ
Status Register Data
Addr = X
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
STANDBY
Check SR6
1 = Programming Suspend
0 = Programming
Completed
0
SR7 =
WRITE
READ ARRAY
1
0
SR2 =
READ
Read array locations other
than that being
programmed
Programming
Completed
WRITE
1
Data = FFh
Addr = X
PROGRAM
RESUME
Data = D0h
Addr =X
Write FFh
Read Data Array
1
No
Done Reading
Yes
Write D0h
Write FFh
Programming
Resumed
Read Data Array
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
33
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 12: BLOCK ERASE Flowchart
BUS OPERATION COMMAND
COMMENTS
WRITE
ERASE BLOCK
Data = 20h
Addr = Block Address
WRITE
ERASE
CONFIRM
Data = D0h
Addr = Block Address
Start
Issue Single BLOCK
ERASE Command 20h,
Block Address
Write Confirm D0h
Block Address
Read Status
Register
No
SR7 =
Suspend Erase
Yes
1
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
The erase confirm byte must follow erase setup.
Full Status
Check if Desired
This device does not support erase queuing.
Full status check can be done after all erase and write sequences
complete. Write FFh after the last operation to reset the device
to read array mode.
Erase Flash
Block(s) Complete
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
Status register data with
the device enabled; OE#
LOW updates SR
Addr = X
Toggling OE# (LOW to HIGH to LOW) updates the status register.
To ensure the availability of correct status, please follow the
timings shown in Figure 20 on page 50. This can be done in place
of issuing the READ STATUS REGISTER command. Repeat for
subsequent ERASE operations.
Suspend
Erase Loop
No
READ
34
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 13: BLOCK ERASE SUSPEND/
RESUME Flowchart
BUS
OPERATION
WRITE
Start
COMMAND
READ
Status Register Data
Addr = X
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
STANDBY
Check SR6
1 = Block Erase Suspend
0 = Block Erase Completed
Write B0h
Read Status
Register
0
WRITE
SR7 =
COMMENTS
ERASE SUSPEND Data = B0h
Addr = X
ERASE RESUME
Data = D0h
Addr = X
1
0
BLOCK ERASE
Completed
SR6 =
1
Read
Read or
Program?
Read Array
Data
No
Program
Program
Loop
Done?
Yes
Write D0h
Write FFh
BLOCK ERASE
Resumed
Read Data Array
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
35
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 14: SET BLOCK LOCK BITS
Flowchart
BUS
OPERATION
COMMAND
COMMENTS
Start
WRITE
SET BLOCK
LOCK BITS
SETUP
Data = 60h
Addr = Block Address
Write 60h,
Block Address
WRITE
SET BLOCK
LOCK BITS
CONFIRM
Data = 01h
Addr = Block Address
Write 01h,
Block Address
READ
Status Register Data
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
Read Status
Register
Repeat for subsequent lock bit operations.
Full status check can be done after each lock bit set operation or
after a sequence of lock bit set operations.
0
SR7 =
Write FFh after the last lock bit set operation to place device in read
array mode.
1
Full Status
Check if Desired
BUS
OPERATION
SET BLOCK LOCK BITs
Complete
1
SR3 =
Voltage Range Error
Check SR3
1= Programming Voltage
Error Detect
STANDBY
Check SR4, SR5
Both 1 = Command
Sequence Error
STANDBY
Check SR4
1 = Set Block Lock Bits Error
SR5, SR4, and SR3 are only cleared by the Clear Status Register
command in cases where multiple lock bits are set before full
status is checked.
0
1
SR4,5 =
Command Sequence
Error
If an error is detected, clear the status register before
attempting retry or other error recovery.
0
1
SR4 =
COMMENTS
STANDBY
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (see above)
COMMAND
SET BLOCK LOCK BITS
Error
0
SET BLOCK LOCK BITS
Successful
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
36
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 15: CLEAR BLOCK LOCK BITS
Flowchart
BUS
OPERATION
COMMAND
COMMENTS
Start
WRITE
CLEAR BLOCK
LOCK BITS
SETUP
Data = 60h
Addr = X
Write 60h
WRITE
CLEAR BLOCK
LOCK BITS
CONFIRM
Data = D0h
Addr = X
Write D0h
READ
Status Register Data
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
Read Status
Register
Write FFh after the CLEAR BLOCK LOCK BITS operation to place
device in read array mode.
0
SR7 =
BUS
OPERATION
1
COMMAND
COMMENTS
Full Status
Check if Desired
STANDBY
CLEAR BLOCK LOCK
BITS Complete
Check SR3
1= Programming Voltage
Error Detect
STANDBY
Check SR4, SR5
Both 1 = Command
Sequence Error
STANDBY
Check SR4
1 = Clear Block Lock Bits
Error
FULL STATUS CHECK PROCEDURE
Read Status Register
Data (see above)
1
SR3 =
SR5, SR4, and SR3 are only cleared by the Clear Status Register
command.
Voltage Range Error
If an error is detected, clear the status register before
attempting retry or other error recovery.
0
1
SR4,5 =
Command Sequence
Error
0
1
SR5 =
CLEAR BLOCK LOCK
BITS Error
0
CLEAR BLOCK LOCK
BITS Successful
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
37
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Figure 16: PROTECTION REGISTER
PROGRAMMING Flowchart
Start
Write C0h
(Protection Register
Program Setup)
BUS OPERATION COMMAND
COMMENTS
WRITE
PROTECTION
PROGRAM
SETUP
Data = C0h
WRITE
PROTECTION
PROGRAM
Data = Data to Program
Addr = Location to Program
READ
Status Register Data
Toggle CE# or OE# to
update status register data
STANDBY
Check SR7
1 = ISM Ready
0 = ISM Busy
Write Protect Register
Address/Data
Read Status
Register
PROTECTION PROGRAM operations can only be addressed within
the protection register address space. Addresses outside the
defined space will return an error.
No
SR7 = 1
Repeat for subsequent programming operations.
Yes
SR full status check can be done after each program or after a
sequence of program operations.
Full Status
Check if Desired
Write FFh after the last program operation to reset device to
read array mode.
PROGRAM
Complete
FULL STATUS CHECK PROCEDURE
BUS OPERATION COMMAND
Read Status Register
Data (see above)
1, 1
SR3, SR4 =
0, 1
SR1, SR4 =
1, 1
SR1, SR4 =
0 xxx1 xxx1 xxvVPEN LOW
0 xxx1 xxx1 xxvProtection
Register
Program
Error
STANDBY
1 xxx0 xxx1 xxvRegister
Locked:
Aborted
SR3, if set during a program attempt, MUST be cleared before
further attempts are allowed by the ISM.
Attempted Program to
Locked Register –
Aborted
SR1, SR3, and SR4 are only cleared by the CLEAR STATUS
REGISTER command, in cases of multiple protection register
program operations, before full status is checked.
PROGRAM
Successful
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
STANDBY
STANDBY
VPEN Range Error
PROTECTION REGISTER
PROGRAMMING Error
COMMENTS
SR1 SR3 SR4
If an error is detected, clear the status register before
attempting retry or other error recovery.
38
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Design Considerations
Five-Line Output Control
mended that systems without separate power and
ground planes attach a 0.1µF ceramic capacitor
between each of the device’s three VCC pins (this
includes VCCQ) and GND. These high-frequency, lowinductance capacitors should be placed as close as
possible to package leads on each Micron Q-Flash
memory device. Additionally, for every eight devices, a
4.7µF electrolytic capacitor should be placed between
VCC and GND at the array’s power supply connection.
Micron provides five control inputs (CE0, CE1, CE2,
OE#, and RP#) to accommodate multiple memory
connections in large memory arrays. This control provides the lowest possible memory power dissipation
and ensures that data bus contention does not occur.
To efficiently use these control inputs, an address
decoder should enable the device (see Table 2 on
page 11) while OE# is connected to all memory devices
and the system’s READ# control line. This ensures that
only selected memory devices have active outputs
while deselected memory devices are in standby
mode. During system power transitions, RP# should
be connected to the system POWERGOOD signal to
prevent unintended writes. POWERGOOD should also
toggle during system reset.
Reducing Overshoots and Undershoots
When Using Buffers or Transceivers
Overshoots and undershoots can sometimes cause
input signals to exceed Flash memory specifications as
faster, high-drive devices such as transceivers or buffers drive input signals to Flash memory devices. Many
buffer/transceiver vendors now carry bus-interface
devices with internal output-damping resistors or
reduced-drive outputs. Internal output-damping
resistors diminish the nominal output drive currents,
while still leaving sufficient drive capability for most
applications. These internal output-damping resistors
help reduce unnecessary overshoots and undershoots
by diminishing output-drive currents. When considering a buffer/transceiver interface design to Flash,
devices with internal output-damping resistors or
reduced-drive outputs should be used to minimize
overshoots and undershoots.
STS and Block Erase, Program, and Lock
Bit Configuration
Polling
As an open drain output, STS should be connected
to VCCQ by a pull-up resistor to provide a hardware
method of detecting block erase, program, and lock bit
configuration completion. It is recommended that a
2.5KΩ resistor be used between STS# and VCCQ. In
default mode, it transitions low after block erase, program, or lock bit configuration commands and returns
to High-Z when the ISM has finished executing the
internal algorithm. See the CONFIGURATION command for alternate configurations of the STS pin. STS
can be connected to an interrupt input of the system
CPU or controller. STS is active at all times. In default
mode, it is also High-Z when the device is in block
erase suspend (with programming inactive), program
suspend, or reset/power-down mode.
VCC, VPEN, and RP# Transitions
If VPEN or VCC falls outside of the specified operating ranges, or RP# is not set to VIH, block erase, program, and lock bit configuration are not guaranteed. If
RP# transitions to VIL during block erase, program, or
lock bit configuration, STS (in default mode) will
remain LOW for a maximum time of tPLPH + tPHRH,
until the RESET operation is complete and the device
enters reset/power-down mode. The aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock bit
configuration. Therefore, block erase and lock bit configuration commands must be repeated after normal
operation is restored. Device power-off or RP# = VIL
clears the status register. The CEL latches commands
issued by system software and is not altered by VPEN or
CEx transitions, or ISM actions. Its state is read array
mode upon power-up, upon exiting reset/powerdown mode, or after VCC transitions below VLKO. VCC
must be kept at or above VPEN during VCC transitions.
Power Supply Decoupling
Device decoupling is required for Flash memory
power switching characteristics. There are three supply current issues to consider: standby current levels,
active current levels, and transient peaks produced by
falling and rising edges of CEx and OE#. Transient current magnitudes depend on the device outputs’ capacitive and inductive loading. Two-line control and
proper decoupling capacitor selection suppresses
transient voltage peaks. Because Micron Q-Flash
memory devices draw their power from three VCC pins
(these devices do not include a VPP pin), it is recom-
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
39
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
After block erase, program, or lock bit configuration, and after VPEN transitions to VPENLK, the CEL
must be placed in read array mode via the READ
ARRAY command if subsequent access to the memory
array is desired. During VPEN transitions, VPEN must be
kept at or below VCC.
or disabling the device inhibits WRITEs. The CEL’s
two-step command sequence architecture provides
added protection against data alteration. In-system
block lock and unlock capability protects the device
against inadvertent programming. The device is disabled when RP# = VIL regardless of its control inputs.
Keeping VPEN below VPENLK prevents inadvertent data
change.
Power-Up/Down Protection
During power transition, the device itself provides
protection against accidental block erasure, programming, or lock bit configuration. Internal circuitry
resets the CEL to read array mode at power-up. A system designer must watch out for spurious writes for
VCC voltages above VLKO when VPEN is active. Because
WE# must be low and the device enabled (see Table 2
on page 11) for a command write, driving WE# to VIH
09005aef80b5a323
MT28F640J3.fm – Rev. N 3/05 EN
Power Dissipation
Designers must consider battery power consumption not only during device operation, but also for data
retention during system idle time. Flash memory’s
non-volatility increases usable battery life because
data is retained when system power is removed.
40
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000 Micron Technology. Inc.
128Mb, 64Mb, 32Mb
Q-FLASH MEMORY
Electrical Specificatons
Table 22: Absolute Maximum Ratings
Note 1
VOLTAGE
Temperature under bias expanded
Storage Temperature
For VCCQ = +2.7V to +3.6V
Voltage on any pin
Short Circuit Output Current
MIN
MAX
UNITS
-40
-65
+85
+125
°C
°C
-2.0V
+5.0
100
V
mA
NOTES
2
3
NOTE:
1. Stresses greater than those listed in Table 22 may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC
and VPEN pins. During transitions, this level may undershoot to -2.0V for periods
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